The present invention is related to input/output(I/O) architecture of a computer system, and more particularly to an interrupt handling subsystem of the I/O architecture.
Today""s computer systems are very advanced, versatile, and sophisticated. Especially these computers are now commonly called upon to accept and process data from a wide variety of Peripheral Component Interconnect (PCI) devices such as network devices, modems, tape drives, disk drives, network controllers, Ethernet, ATM, graphic devices, pointers, keyboards, serial ports and printers via a PCI bus. Generally a bridge device is interposed between different bus schemes and acts as an interface between the bus and main memory/microprocessor (CPU). All write and interrupt operations involving PCI devices are routed to/from a PCI device via the PCI bus and an interrupt line respectively, through the bridge, to a memory controller and to/from the main memory. For example, during an interrupt transfer from the PCI device, the interrupt is translated into one or more write packets and sent to the microprocessor through the bridge and the memory controller. Further, during a data transfer to memory from the PCI device (memory writes), the PCI write operation is translated into one or more packets and sent to the main memory and/or microprocessor through the bridge and the memory controller. Generally all of the interrupts are level-based and level sensitive. Where as most of the new microprocessors want edge-based interrupts, which basically means that when an interrupt is asserted, the processor will then go into its interrupt service routine and service the input, and on the way out it exits the interrupt and clears the interrupt it exits, if the interrupt is still active it immediately jumps back in. Level-based means as long as the interrupt is at that level, the CPU has to go back in to execute the interrupt routine. Where as in the case of edge-based interrupts, all we need is an edge, you need an active occurrence. If the interrupt is not in transition, then the microprocessor does not have to go back to back to execute the interrupt routine. In general the input/output subsystem is connected via a packet or switch based network so that the packet is essentially an edge. An edge is an event that happens. Many of the new microprocessors are actually based on this edge-based interrupts. When there is multiple interrupts within the interrupt line, there is a chance that the microprocessor may not see the transition between the interrupts if the interrupts are level based. In situations like these the standard software solution to this problem would be to pole some register inside the bridge to wait for interrupt line to go high, so that the microprocessor can detect the next interrupt. Polling a bridge register while in the interrupt routine can take a microsecond or two and that""s thousands of processor instruction cycles that the microprocessor is waiting. During this time the microprocessor cannot do anything, because the processor is waiting for the interrupt routine to complete and during this time the processor is not allowing other interrupts to be processed. This is wasting a lot of processor time.
Interrupts are transferred over the same path as memory write operations from PCI devices. If writes contain errors, these errors can corrupt memory or generate false interrupts. Corrupted memory and false interrupt can cause the computer to enter an unrecoverable state.
Thus, there is a need for an improved interrupt detection and translation system and method from the PCI devices on a PCI bus to prevent the computer system from missing an interrupt.
In addition, there is also a need for an improved error detection and containment system from PCI devices on a PCI bus to prevent the computer system from corrupting memory when errors occurs, and allowing the system to recover from the errors. Also there is a need to prevent the computer systems from generating false interrupts due to write errors. Further, there is also a need to increase the uptime of the computer system.
The above-mentioned shortcomings, disadvantages and problems are addressed by the present invention, which will be understood by reading and studying the following specification. The present system provides, among other things, an improved interrupt handling and translation and an improved error detection and containment from PCI devices.
According to one aspect of the present invention, interrupts are received by a bridge device via an interrupt line from one or more PCI devices. Then the bridge device encodes the interrupt with source and destination information, and sends an interrupt write packet to a microprocessor (CPU) through the memory controller to launch an interrupt routine. The interrupt routine services the interrupt and the PCI device negates the interrupt line. At this point, the CPU generates a non-blocking write rather than a blocking read to the bridge device. This write causes the bridge device to check the level of the PCI interrupt line. If the line is asserted (i.e., if the interrupt is still active in the interrupt line), then another write packet is sent by the bridge device, otherwise the interrupt line is negated, and the blocking write is ignored. As a result, the present invention prevents an interrupt from a PCI device from being overlooked, from being missed, or from repeating the interrupt by the PCI device. Furthermore, non-blocking write is used to write the interrupts to the registers contained in the bridge, the processor does not waste any cycles waiting for an interrupt from the bridge.
According to another aspect of the present invention, write transactions are received by a bridge via a Peripheral Component Interconnect (PCI) bus from PCI devices. Then the bridge checks the write transactions for parity errors. Further the bridge encodes the write transactions and the interrupts with the source and destination information and translates them into one or more packets of write requests. Then the bridge device flags the packet of write requests having errors. Then a memory controller coupled to the bridge device checks the write request packets for the error flag. If the flag is not set, then the memory controller transfers the write requests, and if the flag is set, then the memory controller suppresses the write requests, and disables all future write requests and interrupts from the PCI device associated with the write request containing the error. As a result, the present invention prevents the write requests and interrupts from an invalid PCI device from writing to the memory to prevent corrupting the memory in the computer system and stopping the entire input/output subsystem. Further, this also prevents losing of all data in the memory and increases the xe2x80x9cup-timexe2x80x9d of the computer system. Other aspects of the invention will be apparent on reading the following detailed description of the invention and viewing the drawings that form a part thereof.